This invention relates to a process for fabricating metal-oxide-semiconductor field-effect transistors (MOSFETs) having a lightly-doped drain (LDD) structure.
The minimum size of conventional MOSFETs is limited by degradation caused by hot carriers, which are generated by peak electric fields occurring near the channel-drain boundary, particularly when the transistor operates in the saturation region. Such hot carriers become trapped in the gate oxide layer, significantly shortening the lifetime of transistors with minimum dimensions below 1.5 .mu.m. Solutions to this problem have been sought in a variety of lightly-doped drain structures in which a lightly-doped offset area is provided between the channel and the more heavily-doped drain, the offset serving to reduce the peak electric field during transistor operation.
One well-known method of forming a lightly-doped drain first creates the lightly-doped offset area by a doping step performed with the gate electrode as a mask, then adds oxide sidewall spacers to the gate electrode and performs a second doping step at a higher dose to create the source and drain. This method has the disadvantage of increasing the minimum separation between the heavily-doped source and drain by an amount equal to the thickness of the sidewalls, thus enlarging the size of the transistor and reducing its transconductance (g.sub.m). An additional problem is that doping levels adequate to avoid unwanted resistance in the offset area are too high to eliminate the problem of electric field peaking near the interface between the drain offset and the channel.
A second method known as the double-diffused drain implants first phosphorus then arsenic with the gate electrode as a mask. Subsequent heat treatment causes the two impurities to diffuse and create a lightly-doped offset with a graded doping profile, which tends to avoid peaking of the electric field. Diffusion of phosphorus from the edges of the gate, however, leads to well-known short-channel effects, making channel lengths shorter than about 1.5 .mu.m difficult to attain.
A third method, disclosed in Japanese Patent Application Kokai Publication No. 127761/1985, employs a tungsten-silicide gate having tapered sides, which are created by an oxidation step performed at atmospheric pressure. Heavily-doped and lightly-doped source and drain areas are formed in a single high-energy arsenic ion implantation step, the lightly-doped areas being disposed under the tapered sides of the gate electrodes. This method has the disadvantage that the high energy needed to implant arsenic ions through the tapered sides of the gate electrode also drives arsenic deeply into the heavily-doped source and drain regions. As a result, extra isolation is required between adjacent transistors, so it is difficult to create densely integrated devices. Another disadvantage is that tapering reduces the cross-sectional area of the gate electrode, thereby increasing the gate resistance.
A fourth method, disclosed in Japanese Patent Application Kokai Publication No. 170064/1986, employs a tapered polysilicon gate. Otherwise, this method is similar to the third method and suffers from the same disadvantages.
A fifth method, disclosed in the 1987 IEDM Technical Digest published by the Institute of Electrical and Electronics Engineers, pp. 38-41, etches a polysilicon gate electrode into an inverted T-shape, creates lightly-doped regions below the horizontal ends of the inverted T, then adds sidewalls and creates heavily-doped source and drain areas. The result is a gate-drain overlapped LDD structure that has been named the GOLD structure. A disadvantage of the fifth method is the difficulty of controlling the etching process that shapes the polysilicon gate.